Built-in self-test (BIST) consists of circuits manufactured as part of an integrated circuit that enable the verification of some or all of the intern al functionality of the integrated circuit. BIST has many benefits, including reducing the reliance on external test equipment, reducing the time required for test, improving the simplicity of the test interface, and reducing the number input/output pins required for test.
As more and more functionality gets integrated into system-on-chip (SoC) designs, there has been a steady increase in the amount of memory present on such chips. Observers in the semiconductor industry widely believe that this trend will continue. According to the International Technology Roadmap for Semiconductors, almost 90% of chip area is going to comprise various memories by 2014. Because manufacturing yield depends on the quality of test, the clear indication is that SoC manufacturing yield is going to be proportional to the quality of memory test, and in particular MBIST. Of course, this will be true for any chip having significant amounts of memory.
Memory typically has the highest transistor density of the components of a particular chip design. As a result, the power consumption can be very high while accessing memories during MBIST. If memory test power requirement are not incorporated into the design of the power grid of a chip, the heat generated during test may permanently damage the chip. For example if all the memories of a chip are tested in parallel, i.e. all memories are tested at nearly the same time, the power dissipation will be at a maximum, and the generated heat may well destroy the chip. To keep power dissipation under the damage limit during MBIST, memories may be tested serially, that is, each memory tested one at a time until all memories have been tested. Though the resultant heat dissipation will less, performing MBIST serially significantly increases the time required for testing, usually beyond acceptable limits. However, when it is not known in advance whether and how much of MBIST may be performed in parallel, performing such testing serially usually ensures that the chip will not overheat.
Extra hardware inserted on a chip for purposes of test is considered necessary, but otherwise undesirable, by a chip designer because it occupies valuable chip area. An increase in used chip area increases complexity, cost, and time to market of the chip. Moreover, as chip geometries and feature sizes continue to shrink and ever more functionality is integrated onto the chip, the number of wires required to connect the larger number of various circuits also increases. Thus, the test hardware is not only a concern from the area perspective, but also in terms of increased wire routing congestion on the chip. On top of area and congestion, because memories often need to be tested at or near their operation speed, timing is also an important consideration when designing MBIST hardware. MBIST hardware should be physically aware, so that the area overhead, wire routing congestion, and interconnect timing may be optimized.
Presently, there is no suitable technique that may be used to estimate the power, test time, area overhead, wire routing congestion, and interconnect timing for a chip designer, which estimates would allow the chip designer to minimize the test time and area overhead, while preventing excessive wiring congestion and chip damage from excessive power dissipation during MBIST. For example, power dissipation is influenced by many factors for each of the memories under test, including address size of the memory, data width of the memory, the size of the memory multiplexers, and the frequency at which the memory is being tested. In order to determine the power dissipation, presently, a chip designer needs to run an extensive flow of various CAD tools in the design environment. Similarly, the area overhead depends on a number of factors, including the number of controllers, number of devices being shared by a controller, the address width of the memory, and the data width of the memory. To determine the area overhead, the chip designer must insert MBIST hardware into the circuit design and synthesize the design to calculate the area overhead estimate. These approaches are time consuming, increasing cost and time to market.